Technical Q&A's

HW 06 - PCI Bus Performance with Memory Write and Memory Write Invalidate Commands (15-July-95)

Q Does using the Memory Write command instead of the Memory Write Invalidate command when writing a full cache line impact PCI-bus performance?

A Yes. When you use the Memory Write command, you are disconnected by the host bridge every eight bytes. Eight bytes is two data phases on the PCI bus, and this is the width of the PowerPC data bus for a single transaction. Memory Write and Memory Write Invalidate are more efficient, since they transfer a complete cache line (i.e., 32 bytes or eight PCI data phases or one PowerPC burst cycle).

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